TSMC make film for each layer of design. there base layer and metal layers.

it takes about 7 weeks for 40nm to bump out the silicon.

at tsmc, there is wafer sorting, we call it CP test, means chip probe,

there is probe cards with needles to connect to the pads.

CP test(room and hot temperature) will sort out bad dices, the wafer sorting will create a wafer map to record what dice are perfect,

what are totally bad, what are partial bad/good.

wafer sent to SPIL, which a packaging and testing company.

wafer is cut into pieces, perfect and partial good dice are packaged, then final test.

final test will decide the SKU.